Power-on Built-in Self-Test for FPGA

-Built-in self-test (BIST) is a design technique that allows a circuit to test itself. It is a set of structured-test techniques for combinational and sequential logic, memories, multipliers and other embedded logic blocks. BIST consists of a controller, and circuits for input excitation and output validation. A BIST circuit comprises a scan monitor with hold logic and a signature generation element. The hold logic is operable to suspend signature generation in the signature generation element at any desired point in the test sequence. In this project, a new approach for FPGA testing is introduced that exploits the reprogramability of an FPGA to create the BIST logic by configuring it only during off-line testing and during power-on. Hence testability is achieved without any overhead, since the BIST logic "disappears" when the circuit is reconfigured for its normal system operation. A Restartable BIST circuit is designed to monitor fault detection activity during power on with hold logic and a signature generation element. Then it is implemented for the configurable logic blocks in FPGAs.